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ltc1646 1 1646fa compactpci bus removable boards allows safe board insertion and removal from a live, compactpci tm bus controls 3.3v and/or 5v supplies programmable foldback current limit during power-up dual level circuit breakers protect supplies from overcurrent and short-circuit faults local_pci_rst# logic on-chip precharge output biases i/o pins during card insertion and extraction user programmable supply voltage power-up rate 15v high side drive for external n-channel mosfets pwrgd, resetout and fault outputs compactpci dual hot swap controller the ltc ? 1646 is a hot swap tm controller that allows a board to be safely inserted and removed from a live compactpci bus slot. two external n-channel transistors control the 3.3v and 5v supplies. the supplies can be ramped-up in current limit or a programmable rate. elec- tronic circuit breakers protect both supplies against overcurrent fault conditions. the pwrgd output indicates when all of the supply voltages are within tolerance. the off/on pin is used to cycle the board power or reset the circuit breaker. the precharge output can be used to bias the bus i/o pins during card insertion and extraction. pci_rst# is logically combined on-chip with healthy# in order to generate local_pci_rst# which can be used to reset the cpci card logic if either of the supply voltages is not within tolerance. the ltc1646 is available in the 16-pin narrow ssop package. figure 1 mmbt2222a 4.7nf 18 ? 18 ? 12 ? 10 ? 2.7 ? 1.8 ? r3 10 ? 3k r4 10 ? 3k 1k r1 0.005 ? , 1% r2 0.007 ? 1% 1k r5 1k, 5% 10k 10k 3k 1.2k 3v in precharge out 1v 10% i out = 55ma 3v in 3v in 3v sense 5v sense 3v out 3v out 5v out 3.3v 5v in 5v in 5v reset# i/o pci bridge (21154) data bus data bus v(i/o) v(i/o) 0.1 f 0.1 f 0.1 f c1 0.01 f q2 irf7413 q1 irf7413 local_pci_rst# 5v 5a 3.3v 7.6a gate gnd precharge drive resetout timer off/on fault pwrgd resetin ltc1646 15 891071211 5 2 1 613 14 3 4 16 bd_sel# healthy# pci_rst# 1646 f01 data line example compact pci backplane connector (male) compact pci circuit card connector (female) 5v long 5v 3.3v long 3.3v ground i/o pin 1 z1, z2: bzx84c6v2 z2 z1 applicatio s u features typical applicatio u descriptio u , ltc and lt are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltc1646 2 1646fa symbol parameter conditions min typ max units i dd v 5vin supply current off/on = 0v 1.5 4 ma v lko undervoltage lockout 5v in 2.3 2.50 2.7 v 3v in 2.3 2.55 2.7 v v fb foldback current limit voltage v fb = (v 5vin Cv 5vsense ), v 5vout = 0v, timer = 0v 15 20 30 mv v fb = (v 5vin C v 5vsense ), v 5vout = 4v, timer = 0v 50 55 65 mv v fb = (v 3vin C v 3vsense ), v 3vout = 0v, timer = 0v 15 20 30 mv v fb = (v 3vin C v 3vsense ), v 3vout = 2v, timer = 0v 50 55 65 mv v cb circuit breaker trip voltage v cb = (v 5vin C v 5vsense ), v 5vout = 5v, timer open 50 56 65 mv v cb = (v 3vin C v 3vsense ), v 3vout = 3.3v, timer open 50 56 65 mv t oc overcurrent fault response time (v 5vin C v 5vsense ) = 100mv, timer open 10 21 30 s (v 3vin C v 3vsense ) = 100mv, timer open 10 21 30 s t ss short-circuit fault response time (v 5vin C v 5vsense ) = 200mv, timer open 0.145 1 s (v 3vin C v 3vsense ) = 200mv, timer open 0.145 1 s i cp gate pin output current off/on = 0v, v gate = 0v, timer = 0v C18 C13 C8 a off/on = 5v, v gate = 5v, timer = 0v 80 200 300 a off/on = 0v, v gate = 5v, fault = 0v, timer open 4712ma v gate external gate voltage off/on = 0v, i gate = C1 a 12 15 16 v (gate to gnd) off/on = 0v, v 5vin = 3.3v, i gate = C1 a 11 13 15 v v th power good threshold voltage 3v out 2.8 2.9 3.0 v 5v out 4.5 4.65 4.75 v v 3vonly no 5v input mode window voltage v 3vonly = ? v 5vin C v 3vin ? , v 5vout = v 3vout = 3.3v 50 120 200 mv v il input low voltage off/on, resetin, fault 0.8 v order part number t jmax = 125 c, ja = 135 c/w consult ltc marketing for parts specified with wider operating temperature ranges. ltc1646cgn LTC1646IGN absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v 5vin = 5v and v 3vin = 3.3v unless otherwise noted. supply voltages: 5v in , 3v in ............................................... 10v input voltages: (pins 15, 16) ..................... C0.3v to 10v output voltages: (pins 1, 3, 4) .................. C0.3v to 10v analog voltages and currents: (pin 9) .................................... C0.3v to (3v in + 0.3v) (pins 2, 5, 7, 11, 13, 14) ........ C0.3v to (5v in + 0.3v) (pin 10) .......................................................... 20ma operating temperature range: ltc1646c ............................................... 0 c to 70 c ltc1646i .............................................C40 c to 85 c storage temperature range ..................C65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 resetout timer fault pwrgd 5v out gnd 3v out 3v in resetin off/on drive precharge 5v in 5v sense gate 3v sense gn part marking 1646 1646i order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
ltc1646 3 1646fa symbol parameter conditions min typ max units v ih input high voltage off/on, resetin, fault 2v v timer timer threshold voltage v timer , fault = 0v 1.15 1.25 1.35 v i in off/on input current off/on = 5v 0.08 10 a off/on = 0v 0.08 10 a resetin input current resetin = 5v 0.08 10 a resetin = 0v 0.08 10 a 5v sense input current 5v sense = 5v, 5v out = 0v 66 100 a 3v sense input current 3v sense = 3.3v, 3v out = 0v 66 100 a 3v in input current 3v in = 3.3v 460 1000 a 5v out input current 5v out = 5v, off/on = 0v 0.9 1.5 ma 3v out input current 3v out = 3.3v, off/on = 0v 0.9 1.5 ma i timer timer pin current off/on = 0v, v timer = 0v C7 C5 C3 a off/on = 5v, v timer = 5v 6.6 ma r dis 5v out discharge impedance off/on = 5v 120 220 ? 3v out discharge impedance off/on = 5v 120 220 ? v ol output low voltage fault, pwrgd, resetout, i = 2ma 0.25 0.4 v v pxg precharge reference voltage v precharge , v 5vin = 5v and 3.3v 0.90 1.00 1.10 v electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v 5vin = 5v and v 3vin = 3.3v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. typical perfor a ce characteristics uw 5v current foldback profile 3.3v current foldback profile output voltage (v) 0 output current (a) 2 4 5 1646 g01 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r sense = 0.007 ? 1646 g02 12 11 10 9 8 7 6 5 4 3 2 1 0 output voltage (v) 0 output current (a) 2 4 5 13 r sense = 0.005 ? C50 C25 0 25 50 75 100 temperature ( c) supply current (ma) 1646 g03 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 5v in supply current vs temperature
ltc1646 4 1646fa typical perfor a ce characteristics uw 5v in undervoltage lockout voltage vs temperature 3v in undervoltage lockout voltage vs temperature 5v in foldback current limit voltage vs temperature C50 C25 0 25 50 75 100 temperature ( c) undervoltage lockout voltage (v) 1646 g04 2.60 2.55 2.50 2.45 2.40 low-to-high transition high-to-low transition C50 C25 0 25 50 75 100 temperature ( c) undervoltage lockout voltage (v) 1646 g05 2.60 2.55 2.50 2.45 2.40 low-to-high transition high-to-low transition C50 C25 0 25 50 75 100 temperature ( c) foldback current limit voltage (mv) 1646 g06 60 50 40 30 20 10 0 5v out = 4v 5v out = 0v C50 C25 0 25 50 75 100 temperature ( c) foldback current limit voltage (mv) 1646 g07 60 50 40 30 20 10 0 3v out = 2v 3v out = 0v C50 C25 0 25 50 75 100 temperature ( c) circuit breaker trip voltage (mv) 1646 g08 60 59 58 57 56 55 54 53 52 51 50 C50 C25 0 25 50 75 100 temperature ( c) circuit breaker trip voltage (mv) 1646 g09 60 59 58 57 56 55 54 53 52 51 50 C50 C25 0 25 50 75 100 temperature ( c) overcurrent fault response time ( s) 1646 g10 22.00 21.75 21.50 21.25 21.00 20.75 20.50 20.25 20.00 C50 C25 0 25 50 75 100 temperature ( c) short-circuit fault response time (ns) 1646 g11 170 160 150 140 130 120 110 100 C50 C25 0 25 50 75 100 temperature ( c) gate current ( a) 1646 g12 C10 C11 C12 C13 C14 C15 3v in foldback current limit voltage vs temperature 5v in circuit breaker trip voltage vs temperature 3v in circuit breaker trip voltage vs temperature 5v in /3v in overcurrent fault response time vs temperature 5v in /3v in short-circuit fault response time vs temperature gate current vs temperature
ltc1646 5 1646fa typical perfor a ce characteristics uw gate i sink vs temperature gate voltage vs temperature power good threshold voltage vs temperature (3v out ) power good threshold voltage vs temperature (5v out ) timer threshold voltage vs temperature 5v sense input current vs temperature 3v sense input current vs temperature 3v in input current vs temperature timer current vs temperature C50 C25 0 25 50 75 100 temperature ( c) gate i sink (ma) 1646 g13 10 9 8 7 6 5 fault = 0v C50 C25 0 25 50 75 100 temperature ( c) gate voltage (v) 1646 g14 15.5 15.0 14.5 14.0 13.5 13.0 12.5 5v in = 5v i = C1 a 5v in = 3.3v C50 C25 0 25 50 75 100 temperature ( c) power good threshold voltage (v) 1646 g15 3.00 2.95 2.90 2.85 2.80 C50 C25 0 25 50 75 100 temperature ( c) power good threshold voltage (v) 1646 g16 4.75 4.70 4.65 4.60 4.55 4.50 C50 C25 0 25 50 75 100 temperature ( c) timer threshold voltage (v) 1646 g17 1.30 1.28 1.26 1.24 1.22 1.20 C50 C25 0 25 50 75 100 temperature ( c) 5v sense input current ( a) 1646 g18 70 69 68 67 66 65 64 63 62 61 60 C50 C25 0 25 50 75 100 temperature ( c) 3v sense input current ( a) 1646 g19 70 69 68 67 66 65 64 63 62 61 60 C50 C25 0 25 50 75 100 temperature ( c) 3v in input current ( a) 1646 g20 480 475 470 465 460 455 450 445 C50 C25 0 25 50 75 100 temperature ( c) timer current ( a) 1646 g21 C4.00 C4.25 C4.50 C4.75 C5.00 C5.25 C5.50 C5.75 C6.00
ltc1646 6 1646fa pwrgd (pin 4) :open drain power good digital output. connect the cpci healthy# signal to the pwrgd pin. pwrgd remains low while v 3vout 2.9v and v 5vout 4.65v. when either of the supplies falls below its power good threshold voltage, pwrgd will go high after a 50 s deglitching time. 5v out (pin 5): 5v output sense. the pwrgd pin will not pull low until the 5v out pin voltage exceeds 4.65v. if no 5v input supply is available, tie the 5v out pin to the 3v out pin in order to disable the 5v out power good function. gnd (pin 6): chip ground 3v out (pin 7): 3.3v output sense. the pwrgd pin will not pull low until the 3v out pin voltage exceeds 2.90v. if no 3.3v input supply is available, tie the 3v out pin to the 5v out pin. 3v in (pin 8): 3.3v supply sense input. an undervoltage lockout circuit prevents the switches from turning on when the voltage at the 3v in pin is less than 2.5v. if no 3.3v input supply is available, connect a diode between 5v in and 3v in (tie anode to 5v in and cathode to 3v in ). see figure 11. resetout (pin 1): open drain digital output. connect the cpci local_pci_rst# signal to the resetout pin. resetout is the logical combination of resetin and pwrgd (see table 4). timer (pin 2): current fault inhibit timing input. connect a capacitor from timer to gnd. with the chip turned off, the timer pin is internally held at gnd. when the chip is turned on, a 5 a pull-up current source is connected to timer. current limit and voltage compliance faults will be ignored until the voltage at the timer pin is greater than 1.25v. fault (pin 3): open drain digital i/o. fault is pulled low when a current limit fault is detected. faults are ignored while the voltage at the timer pin is less than 1.25v. once the timer cycle is complete, fault will pull low and the chip will latch off in the event of an overcurrent fault. the chip will remain latched in the off state until the off/on pin is cycled high then low or the power is cycled. forcing the fault pin low with an external pull-down will cause the chip to be latched into the off state after a 21 s deglitching time. typical perfor a ce characteristics uw resetout, pwrgd and fault output low voltage vs i sink 5v out /3v out discharge impedance vs temperature C50 C25 0 25 50 75 100 temperature ( c) 3v out /5v out discharge impedance ( ? ) 1646 g23 180 160 140 120 100 80 60 40 20 0 01 2 3 4 5 i sink (ma) output low voltage (v) 1646 g22 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 90 c 25 c C45 c uu u pi fu ctio s
ltc1646 7 1646fa uu u pi fu ctio s 3v sense (pin 9): 3.3v current limit set. with a sense resistor placed in the supply path between 3v in and 3v sense , the gate pin voltage will be adjusted to maintain a constant voltage across the sense resistor and a con- stant current through the switch while the timer pin voltage is less than 1.25v. a foldback feature makes the current limit decrease as the voltage at the 3v out pin approaches gnd. when the timer pin voltage exceeds 1.25v, the circuit breaker function is enabled. if the voltage across the sense resistor exceeds 56mv, the circuit breaker is tripped after a 21 s time delay. in the event the sense resistor voltage exceeds 150mv, the circuit breaker trips immediately and the chip latches off. to disable the 3.3v current limit, 3v sense and 3v in can be shorted together. gate (pin 10): high side gate drive for the external 3.3v and 5v n-channel pass transistors. requires an external series rc network for the current limit loop compensation and setting the minimum ramp-up rate. during power-up, the slope of the voltage rise at the gate is set by the 13 a current source connected to the internal charge pump and the external capacitor connected to gnd or by the 3.3v or 5v current limit and the bulk capacitance on the 3v out or 5v out supply lines. during power-down, the slope of the ramp down voltage is set by the 200 a current source connected to gnd and the external gate capacitor. the voltage at the gate pin will be modulated to maintain a constant current when either the 3v or 5v supplies go into current limit while the timer pin voltage is less than 1.25v. if a current fault occurs after the timer pin voltage exceeds 1.25v, the gate pin is immediately pulled to gnd. 5v sense (pin 11): 5v current limit set. with a sense resistor placed in the supply path between 5v in and 5v sense , the gate pin voltage will be adjusted to maintain a constant voltage across the sense resistor and a con- stant current through the switch while the timer pin voltage is less than 1.25v. a foldback feature makes the current limit decrease as the voltage at the 5v out pin approaches gnd. when the timer pin voltage is greater than 1.25v, the circuit breaker function is enabled. if the voltage across the sense resistor exceeds 56mv but is less than 150mv, the circuit breaker is tripped after a 21 s time delay. in the event the sense resistor voltage exceeds 150mv, the circuit breaker trips immediately and the chip latches off. to disable the 5v current limit, short 5v sense and 5v in together. 5v in (pin 12): 5v supply sense input. an undervoltage lockout circuit prevents the gate pin voltage from ramping up when the voltage at the 5v in pin is less than 2.5v. if no 5v input supply is available, tie the 5v in pin to the 3v in pin. precharge (pin 13): precharge monitor input. an on- chip error amplifier with a 1v reference servos the drive pin voltage to keep the precharge node at 1v. if the precharge function is not being used, tie the precharge pin to gnd. drive (pin 14): precharge base drive output. provides base drive for an external npn emitter-follower which in turn biases the precharge node. if the precharge func- tion is not being used, allow the drive pin to float. off/on (pin 15): digital input. connect the cpci bd_sel# signal to the off/on pin. when the off/on pin is pulled low, the gate pin is pulled high by a 13 a current source. when the off/on pin is pulled high the gate pin will be pulled to ground by a 200 a current source. the off/on pin is also used to reset the electronic circuit breaker. if the off/on pin is cycled high and low following the trip of the circuit breaker, the circuit breaker is reset, and a normal power-up sequence will occur. resetin (pin 16): digital input. connect the cpci pci_rst# signal to the resetin pin. pulling resetin low will cause the resetout pin to pull low.
ltc1646 8 1646fa test diagra w ti i g diagra s w u w v 3vonly no 5v input mode window voltage t oc overcurrent fault detect t sc short-circuit fault detect 5v or 3.3v 100mv fault t oc 1v v 5vsense or v 3vsense fall time 1 s, 5v in = 5v, 3v in = 3.3v 1646 t02 5v or 3.3v 200mv fault t sc 1v v 5vsense or v 3vsense fall time 30ns, 5v in = 5v, 3v in = 3.3v 1646 t03 Cv 3vonly v 3vonly 5v 0v pwrgd v 5vin 3.3v 1646 t01 v 3vonly = ? 5v in C 3v in ? 5v out = 3v out = 3.3v, 3v in = 3.3v
ltc1646 9 1646fa hot circuit insertion when a circuit board is inserted into a live compactpci (cpci) slot, the supply bypass capacitors on the board can draw huge supply transient currents from the cpci power bus as they charge up. the transient currents can cause glitches on the power bus, causing other boards in the system to reset. the ltc1646 is designed to turn a boards supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live cpci slot without glitching the system power supplies. the chip also pro- tects the supplies from shorts, precharges the bus i/o pins during insertion and extraction and monitors the supply voltages. block diagra w timer 2 3v out 7 5v out 5 C + +C q2 q3 200 a 13 a gate 5v out 55mv 150mv v gg 10 5v sense 11 5v in 12 C + +C +C 2.5v uvl C + +C 3v out 55mv 150mv c p3 ref 3v sense 9 3v in 8 resetout 1 C + C + +C +C 2.5v uvl q4 1v c p4 ref C + C + resetin 16 pwrgd 4 q6 fault 3 q7 off/on 15 5 a 5v in gnd 6 drive 14 precharge 1646 bd 13 logic q1 q5 applicatio s i for atio wu u u the ltc1646 is specifically designed for cpci applica- tions where the chip resides on the plug-in board. ltc1646 feature summary 1. allows safe board insertion and removal from a cpci backplane. 2. controls 5v and 3.3v cpci supplies. 3. current limit during power-up: the supplies are allowed to power up in current limit. this allows the chip to power up boards with widely varying capacitive loads without tripping the circuit breaker. the maximum allowable power-up time is programmable using the timer pin and an external capacitor.
ltc1646 10 1646fa applicatio s i for atio wu u u the main 3.3v and 5v inputs to the ltc1646 come from the medium length power pins. the long 3.3v, 5v connec- tor pins are shorted to the medium length 5v and 3.3v connector pins on the cpci plug-in card and provide early power for the ltc1646s precharge circuitry, the v(i/o) pull-up resistors and the pci bridge chip. the bd_sel# signal is connected to the off/on pin while the pwrgd pin is connected to the healthy# signal. the healthy# signal is combined with the pci_rst# signal on-chip to generate the local_pci_rst# signal which is available at the resetout pin. the power supplies are controlled by placing external n-channel pass transistors in the 3.3v and 5v power paths. resistors r1 and r2 provide current fault detection and r5 and c1 provide current control loop compensation. resistors r3 and r4 prevent high frequency oscillations in q1 and q2. when the cpci card is inserted, the long 5v and 3.3v connector pins and gnd pins make contact first. the ltc1646s precharge circuit biases the bus i/o pins to 1v during this stage of the insertion (figure 2). the 5v and 3.3v medium length pins make contact during the next stage of insertion, but the slot power is disabled as long as the off/on pin is pulled high by the 1.2k pull-up resistor to v(i/o). during the final stage of board insertion, the bd_sel# short connector pin makes contact and the off/on pin can be pulled low. this enables the pass transistors to turn on and a 5 a current source is con- nected to the timer pin. the current in each pass transistor increases until it reaches the current limit for each supply. the 5v and 3.3v supplies are then allowed to power up based on one of the following power-up rates: dv dt a c or i c or i c limit v load vout limit v load vout = == 13 1 5 5 3 3 ,, () () () () (1) whichever is slower. current limit faults are ignored while the timer pin voltage is ramping up and is less than 1.25v. once both supply voltages are within tolerance, healthy# will pull low and local_pci_rst# is free to follow pci_rst#. 4. programmable foldback current limit: a programmable analog current limit with a value that depends on the output voltage. if the output is shorted to ground, the current limit drops to keep power dissipation and supply glitches to a minimum. 5. dual-level, programmable 5v and 3.3v circuit breakers: this feature is enabled when the timer pin voltage exceeds 1.25v. if either supply exceeds current limit for more than 21 s, the circuit breaker will trip, the supplies will be turned off, and the fault pin is pulled low. in the event that either supply exceeds three times the set current limit, all supplies will be turned off and the fault pin is pin is pulled low without delay. 6. 15v high side drive for external 3.3v and 5v n-channel mosfets. 7. pwrgd output: monitors the voltage status of the supply voltages. 8. pci_rst# combined on-chip with healthy# to create local_pci_rst# output. if healthy# deasserts, local_pci_rst# is asserted independent of pci_rst#. 9. precharge output: on-chip reference and amplifier pro- vide 1v for biasing bus i/o connector pins during cpci card insertion and extraction. 10. space saving 16-pin ssop package. pci power requirements cpci systems may require up to four power rails: 5v, 3.3v, 12v and C12v. the ltc1646 is designed for cpci applica- tions which only use the 5v and/or 3.3v supplies. the tolerance of the supplies as measured at the components on the plug-in card is summarized in table 1. table 1. pci power supply requirements supply tolerance capacitive load 5v 5v 5% < 3000 f 3.3v 3.3v 0.3v < 3000 f power-up sequence the ltc1646 is specifically designed for hot swapping cpci boards. the typical application is shown in figure 1.
ltc1646 11 1646fa power-down sequence when bd_sel# is pulled high, a power-down sequence begins (figure 3). internal switches are connected to each of the output supply voltage pins to discharge the bypass capacitors to ground. the timer pin (pin 2) is immediately pulled low. the gate pin (pin 10) is pulled down by a 200 a current source to prevent the load currents on the 3.3v and 5v supplies from going to zero instantaneously in order to prevent glitching the power supply voltages. when either of the output voltages dips below its threshold, healthy# pulls high and local_pci_rst# will be asserted low. once the power-down sequence is complete, the cpci card may be removed from the slot. during extraction, the precharge circuit will continue to bias the bus i/o pins at 1v until the 5v and 3.3v long connector pin connections are separated. timer during a power-up sequence, a 5 a current source is connected to the timer pin and current limit faults are ignored until the voltage exceeds 1.25v. this feature allows the chip to power up cpci boards with widely varying capacitive loads on the supplies. the power-up time for either of the two outputs is given by: txv cxv ii on out load xvout out limit xvout load xvout ()? ? C () () () = 2 (2) where xv out = 5v out or 3v out . for example, for c load (5v out ) = 2000 f, i limit = 7a, and i load = 5a, the 5v out turn-on time will be ~10ms. by substituting the variables in equation 2 with the appropriate values, the turn-on time for the 3v out output can also be calculated. the timer period should be set longer than the maximum supply turn-on time but short enough to not exceed the maximum safe operating area of the pass transistor during a short-circuit. the timer period for the ltc1646 is given by: t cv a timer timer = ?. 125 5 (3) as a design aid, the timer period as a function of the timing capacitor using standard values from 0.01 f to 1 f is shown in table 2. 20ms/div gate 10v/div 5v out 3v out 5v/div timer 5v/div bd_sel# 5v/div healthy# 5v/div lcl_pci_rst# 5v/div precharge 5v/div 1646 f02 gate 10v/div 5v out 3v out 5v/div timer 5v/div bd_sel# 5v/div healthy# 5v/div lcl_pci_rst# 5v/div precharge 5v/div 10ms/div 1646 f03 figure 2. normal power-up sequence figure 3. normal power-down sequence applicatio s i for atio wu uu
ltc1646 12 1646fa applicatio s i for atio wu uu figure 4. power-up into a short on 3.3v output gate 5v/div 5v out 3v out 2v/div timer 1v/div bd_sel# 5v/div lcl_pci_rst# 5v/div healthy# 5v/div fault 5v/div 10ms/div 1646 f04 table 2. t timer vs c timer c timer t timer c timer t timer 0.01 f 2.5ms 0.22 f 55ms 0.022 f 5.5ms 0.33 f 82.5ms 0.033 f 8.25ms 0.47 f 118ms 0.047 f 11.8ms 0.68 f 170ms 0.068 f 17ms 0.82 f 205ms 0.082 f 20.5ms 1 f 250ms 0.1 f 25ms the timer pin is immediately pulled low when bd_sel# goes high. short-circuit protection during a normal power-up sequence, if the timer pin is done ramping and a supply is still in current limit, all of the pass transistors will be immediately turned off and fault (pin 3) will be pulled low as shown in figure 4. in order to prevent excessive power dissipation in the pass transistors and to prevent voltage spikes on the supplies during short-circuit conditions, the current limit on each supply is designed to be a function of the output voltage. as the output voltage drops, the current limit decreases. unlike a traditional circuit breaker function where huge currents can flow before the breaker trips, the current foldback feature assures that the supply current will be kept at a safe level and prevents voltage glitches at the input supply when powering up into a short circuit. after power-up (timer pin voltage >1.25v), the 5v and 3.3v supplies are protected from overcurrent and short- circuit conditions by dual-level circuit breakers. if the sense resistor voltage of either supply current exceeds 56mv but is less than 150mv, an internal timer is started. if the supply is still overcurrent after 21 s, the circuit breaker trips and both supplies are turned off (figure 5). 5v in C5v sense 50mv/div gate 10v/div fault 5v/div 10 s/div 1646 f05 figure 5. overcurrent fault on 5v if a short-circuit occurs and the sense resistor voltage of either supply current exceeds 150mv, the circuit breakers trip without delay and the chip latches off (figure 6). the chip will stay in the latched-off state until off/on (pin 15) is cycled high then low, or the 5v in (pin 12) power supply is cycled. the current limit and the foldback current level for the 5v and 3.3v outputs are both a function of the external sense resistor (r1 for 3v out and r2 for 5v out , see figure 1). as shown in figure 1, a sense resistor is connected between
ltc1646 13 1646fa applicatio s i for atio wu uu 5v in (pin 12) and 5v sense (pin 11) for the 5v supply. for the 3.3v supply, a sense resistor is connected between 3v in (pin 8) and 3v sense (pin 9). the current limit and the current foldback current level are given by equations 4 and 5: i mv r i mv r limit xvout sense xvout foldback xvout sense xvout () () () () = = 55 20 (5) where xv out = 5v out or 3v out . as a design aid, the current limit and foldback level for commonly used values for r sense is shown in table 3. table 3. i limit(xvout) and i foldback(xvout) vs r sense r sense ( ? )i limit(xvout) i foldback(xvout) 0.005 11a 4a 0.006 9.2a 3.3a 0.007 7.9a 2.9a 0.008 6.9a 2.5a 0.009 6.1a 2.2a 0.01 5.5a 2a where xv out = 3v out or 5v out . 5v in C5v sense 100mv/div gate 10v/div fault 5v/div 5 s/div 1646 f06 (4) figure 6. short-circuit fault on 5v 4 3 2 1 + C 5v in 5v in r sense 5v sense v cb v cb(max) = 65mv v cb(nom) = 56mv v cb(min) = 50mv 12 11 i load(max) ltc1646* *additional details omitted for clarity 1646 f07 C + figure 7. circuit breaker equivalent circuit for calculating r sense calculating r sense an equivalent circuit for one of the ltc1646s circuit breakers useful in calculating the value of the sense resistor is shown in figure 7. to determine the most appropriate value for the sense resistor first requires the maximum current required by the load under worst-case conditions. two other parameters affect the value of the sense resis- tor. first is the tolerance of the ltc1646s circuit breaker threshold. the ltc1646s nominal circuit breaker threshold is v cb(nom) = 56mv; however, it exhibits a C6mv/+9mv tolerance due to process variations. second is the tolerance (rtol) in the sense resistor. sense resistors are available in rtols of 1%, 2% and 5% and exhibit temperature coefficients of resistance (tcrs) between 75ppm/ c and 100ppm/ c. how the sense resistor changes as a function of temperature depends on the i 2 r power being dissipated by it. the first step in calculating the value of r sense is based on i trip(max) and the lower limit for the circuit breaker threshold, v cb(min) . the maximum value for r sense in this case is expressed by equation 6: r v i sense max cb min trip max () () () = (6) the second step is to determine the nominal value of the sense resistor which is dependent on its tolerance
ltc1646 14 1646fa applicatio s i for atio wu uu (rtol = 1%, 2% or 5%) and standard sense resistor values. equation 7 can be used to calculate the nominal value from the maximum value found by equation 6: r r rtol sense nom sense max () () = + ? ? ? ? ? ? 1 100 (7) often, the result of equation 7 may not yield a standard sense resistor value. in this case, two sense resistors with the same rtol can be connected in parallel to yield r sense(nom) . the last step requires calculating a new value for i trip(max) (i trip(max, new) ) based on a minimum value for r sense (r sense(min) ) and the upper limit for the circuit breaker threshold, v cb(max) . should the calculated value for i trip(max, new) be much greater than the design value for i trip(max) , a larger sense resistor value should be selected and the process repeated. the new value for i trip(max, new) is given by equation 8: i v r where r r rtol trip max new cb max sense min sense min sense nom (,) () () () ( ) () ?C = = ? ? ? ? ? ? ? ? ? ? ? ? 8 1 100 example : a 5v supply exhibits a nominal 5a load with a maximum load current of 6.8a (i load(max) = 6.8a), and sense resistors with 5% rtol will be used. according to equation 6, v cb(min) = 50mv and r sense(max) is given by: r v i mv a sense max cb min trip max () () () . . === ? 50 68 0 0074 the nominal sense resistor value is (equation 7): r r rtol sense nom sense max () () . . = + ? ? ? ? ? ? = ? + ? ? ? ? ? ? = ? 1 100 0 0074 1 5 100 0 007 and the new current-limit trip point is equation 8: i v r v r rtol mv a trip max new cb max sense min cb max sense n m (,) () () () () ?C . . == ? ? ? ? ? ? ? ? ? ? ? ? == 0 1 100 65 0 0065 98 since i trip(max, new) > i load(max) , a larger value for r sense should be selected and the process repeated again to lower i trip(max, new) without substantially affecting i load(max) . output voltage monitor the status of both 5v and 3.3v output voltages is moni- tored by the power good function. in addition, the pci_rst# signal is logically combined on-chip with the healthy# signal to create local_pci_rst# (see table 4). table 4. local_pci_rst# truth table pci_rst# healthy# local_pci_rst# lo lo lo lo hi lo hi lo hi hi hi lo if either of the output voltages drop below the power good threshold for more than 50 s, the healthy# signal will be pulled high and the local_pci_rst# signal will be pulled low. precharge the precharge input and drive output pins are in- tended for use in generating the 1v precharge voltage that is used to bias the bus i/o connector pins during board insertion. the ltc1646 is also capable of generating precharge voltages other than 1v. figure 8 shows a circuit that can be used in applications requiring a precharge voltage less than 1v. the circuit in figure 9 can be used for applications that need precharge voltages greater than 1v. table 5 lists suggested resistor values for r1 and r2 vs precharge voltage for the application circuits shown in figures 8 and 9.
ltc1646 15 1646fa figure 10. 3.3v supply only typical application figure 8. precharge voltage <1v application circuit applicatio s i for atio wu uu mmbt2222a 4.7nf 18 ? 18 ? 10 ? 10 ? 3k 3k 1k 0.005 ? 1% 1k 12 ? 1k 10k 1k 3k 1.2k 3v in precharge out 1v 10% i out = 55ma 3v in 3v in 3v sense 5v sense 3v out 3v out 5v out 3.3v 5v in reset# i/o pci bridge (21154) data bus data line example v(i/o) v(i/o) 0.1 f 0.1 f 0.010 f irf7413 local_pci_rst# 3.3v out 7.6a gate gnd precharge drive resetout timer off/on fault pwrgd resetin ltc1646 15 891071211 5 2 1 613 14 3 4 16 1646 f10 z1: bzx84c6v2 z1 data bus bd_sel# healthy# pci_rst# compact pci backplane connector (male) compact pci circuit card connector (female) 3.3v long 3.3v ground i/o pin 1 4 3 2 1 1.8 ? mmbt2222a 4.7nf 18 ? r1 r2 1k 12 ? 3v in precharge out 1646 f08 gnd precharge drive ltc1646* 61314 *additional details omitted for clarity v precharge = ? 1v r1 r1 + r2 mmbt2222a 4.7nf 18 ? r1 r2 1k 12 ? 3v in precharge out 1646 f09 gnd precharge drive ltc1646* 613 14 *additional details omitted for clarity v precharge = ? 1v r1 + r2 r1 figure 9. precharge voltage >1v application circuit other compactpci applications the ltc1646 can be easily configured for applications where no 5v supply is present by simply tying the 5v in and 5v sense pins to the 3v in pin and tying the 5v out pin to the 3v out pin (figure 10). table 5. r1 and r2 resistor values vs precharge voltage v precharge r1 r2 v precharge r1 r2 1.5v 18 ? 9.09 ? 0.9v 16.2 ? 1.78 ? 1.4v 18 ? 7.15 ? 0.8v 14.7 ? 3.65 ? 1.3v 18 ? 5.36 ? 0.7v 12.1 ? 5.11 ? 1.2v 18 ? 3.65 ? 0.6v 11 ? 7.15 ? 1.1v 18 ? 1.78 ? 0.5v 9.09 ? 9.09 ? 1v 18 ? 0 ?
ltc1646 16 1646fa figure 11. 5v supply only typical application figure 12. bd_sel# pushbutton toggle switch applicatio s i for atio wu uu if no 3.3v supply is present, figure 11 illustrates how the ltc1646 should be configured. first, 3v sense (pin 9) is connected to 3v in (pin 8), 3v out (pin 7) is connected to 5v out (pin 5) and the ltc1646s 3v in pin is connected through a diode (bav16w) to 5v in . for applications where the bd_sel# connector pin is typically grounded on the backplane, the circuit in figure 12 allows the ltc1646 to be reset simply by pressing a pushbutton switch on the cpci plug-in board. this arrangement eliminates the requirement to extract and reinsert the cpci board in order to reset the ltc1646s circuit breakers. overvoltage transient protection good engineering practice calls for bypassing the supply rail of any analog circuit. bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large-value bulk bypass capacitors per supply rail. if power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or pc trace inductance working against the supply bypass capacitors. the opposite is true for ltc1646 hot swap circuits mounted on plug-in cards. in most cases, there is no supply bypass capacitor present on the powered 3.3v or 5v side of the mosfet switch. an abrupt connection, produced by inserting the board into a backplane connec- tor, results in a fast rising edge applied on the 3.3v and the 5v line of the ltc1646. 2.7 ? 10 ? 0.007 ? 1k 3v in 3v sense 5v sense gate 5v out 3v out 5v in 5v in 0.1 f 0.01 f irf7413 5v out ltc1646 8 9 12 11 10 5 7 6 bav16w 1646 f11 gnd compact pci backplane connector (male) compact pci circuit card connector (female) gnd 5v long 5v 4 3 2 1 z1: bzx84c6v2 z1 bd_sel# 1k 100 ? long gnd 15 6 off/on ltc1646 gnd v(i/0) push- button switch 1646 f12 1.2k compact pci backplane connector (male) compact pci circuit card connector (female)
ltc1646 17 1646fa applicatio s i for atio wu uu figure 14. recommended layout for transient protection components 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vias to gnd plane 3v in gnd ltc1646* *additional details omitted for clarity drawing is not to scale! 1646 f14 5v in tz1 tz2 c2 c3 since there is no bulk capacitance to damp the parasitic trace inductance, supply voltage transients excite para- sitic resonant circuits formed by the power mosfet capacitance and the combined parasitic inductance from the wiring harness, the backplane and the circuit board traces. these ringing transients appear as a fast edge on the 3.3v or 5v supply, exhibiting a peak overshoot to 2.5 times the steady-state value followed by a damped sinu- soidal response whose duration and period is dependent on the resonant circuit parameters. since the absolute maximum supply voltage of the ltc1646 is 10v, transient protection against 3.3v and 5v supply voltage spikes and ringing is highly recommended. in these applications, there are two methods for eliminat- ing these supply voltage transients: using zener diodes to clip the transient to a safe level and snubber networks. snubbers are rc networks whose time constants are large enough to safely damp the inductance of the boards parasitic resonant circuits. as a starting point, the shunt capacitors in these networks are chosen to be 10 to 100 the power mosfets c oss under bias. the value of the series resistor (r6 and r7 in figure 13) is then chosen to be large enough to damp the resulting series r-l-c circuit and typically ranges from 1 ? to 10 ? . note that in all figure 13. place transient protection device close to the ltc1646 c1 0.01 f c2 0.1 f c3 0.1 f 3v in v in2 3.3v v in1 5v 3v sense 8 3v out 7 5v in 12 5v out 5 5v sense 11 9 gate 10 r3 10 ? r4 10 ? 5v out at 5a 3v out at 7.6a r5 1k r1 0.005 ? q2 irf7413 q1 irf7413 r2 0.007 ? z1 z2 ltc1646** 1646 f13 gnd 6 z1, z2: bzx84c6v2 **additional details omitted for clarity r6 2.7 ? long 5v r7 1.8 ? long 3.3v ltc1646 circuit schematics, zener diodes and snubber networks have been added to each 3.3v and 5v supply rail and should be used always. these protection networks should be mounted very close to the ltc1646s supply voltage using short lead lengths to minimize lead induc- tance. this is shown schematically in figure 13 and a recommended layout of the transient protection devices around the ltc1646 is shown in figure 14.
ltc1646 18 1646fa table 6. n-channel power mosfet selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8 on semiconductor r ds(on) = 0.1 ? 2 to 5 mmsf5n02hd single n-channel so-8 on semiconductor r ds(on) = 0.025 ? 5 to 10 mtb50n06v single n-channel dd pak on semiconductor r ds(on) = 0.028 ? 5 to 10 irf7413 single n-channel so-8 international rectifier r ds(on) = 0.01 ? 5 to 10 si4410dy single n-channel so-8 vishay-siliconix r ds(on) = 0.01 ? table 7. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r055f 0.055 ? , 0.5w, 1% resistor irc-tt wsl1206r055 vishay-dale 2a lr120601r028f 0.028 ? , 0.5w, 1% resistor irc-tt wsl1206r028 vishay-dale 5a lr120601r011f 0.011 ? , 0.5w, 1% resistor irc-tt wsl2010r011 vishay-dale 7.6a wsl2512r007 0.007 ? , 1w, 1% resistor vishay-dale 10a wsl2512r005 0.005 ? , 1w, 1% resistor vishay-dale pcb layout considerations for proper operation of the ltc1646s circuit breaker function, a 4-wire kelvin connection to the sense resistors is highly recommended. a recommended pcb layout for the sense resistor, the power mosfet, and the gate drive components around the ltc1646 is illustrated in figure 15. in hot swap applications where load currents can reach 10a, narrow pcb tracks exhibit more resistance than wider tracks and operate at more elevated tempera- tures. since the sheet resistance of 1 ounce copper foil is approximately 0.5m ? / , track resistances add up quickly in high current applications. thus, to keep pcb track resistance and temperature rise to a minimum, the sug- gested trace width in these applications for 1 ounce copper foil is 0.03" for each ampere of dc current. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the pc board. for 1 ounce copper foil plating, a general rule is 1a of dc current per via, making sure the via is properly dimensioned so that solder completely fills any void. for other plating thicknesses, check with your pcb fabrication facility. power mosfet and sense resistor selection table 6 lists some current mosfet transistors that are available and table 7 lists some current sense resistors that can be used with the ltc1646s circuit breakers. table 8 lists supplier web site addresses for discrete component mentioned throughout the ltc1646 data sheet. applicatio s i for atio wu u u
ltc1646 19 1646fa applicatio s i for atio wu u u table 8. manufacturers?web site manufacturer web site international rectifier www.irf.com on semiconductor www.onsemi.com irc-tt www.irctt.com vishay-dale www.vishay.com vishay-siliconix www.vishay.com diodes, inc. www.diodes.com information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) package descriptio u gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc1646 20 1646fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2000 lt 1205 rev a ?printed in usa related parts part number description comments ltc1421 hot swap controller dual supplies from 3v to 12v, additionally C12v ltc1422 hot swap controller single supply hot swap in so-8 from 3v to 12v lt1640al/lt1640ah negative voltage hot swap controllers in so-8 negative high voltage supplies from C10v to C 80v lt1641/lt1641-1 positive voltage hot swap controller in so-8 supplies from 9v to 80v, autoretry/latches off ltc1642 fault protected hot swap controller 3v to 15v, overvoltage protection up to 33v ltc1643l/ltc1643l-1/ltc1643h pci bus hot swap controllers 3.3v, 5v, 12v, C12v supplies for pci bus ltc1644 compactpci hot swap controller 3.3v, 5v, 12v local reset logic and precharge ltc1645 2-channel hot swap controller operates from 1.2v to 12v, power sequencing ltc1647 dual hot swap controller dual on pins for supplies from 3v to 15v ltc4211 hot swap controller with multifunction current control single supply, 2.5v to 16.5v, msop figure 15. recommended layout for power mosfet, sense resistor, and gate components 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1646* current flow to source *additional details omitted for clarity drawing is not to scale! 1646 f15 track width w: 0.03" per ampere on 1 oz cu foil d d d d g s s s current flow to load current flow to load sense resistor so-8 via to gnd gnd gnd v out 5v v in 5v via r3 r5 c1 c timer w w w typical applicatio u

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